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[Other resource] 异步FIFO存储器的控制设计

Description: 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
Platform: | Size: 6655 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[ARM-PowerPC-ColdFire-MIPS] FIFO_Buffer

Description: 同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序，erilog编写~具有较强的参考价值~ -Synchronous and asynchronous sequential circuits fifo source and test procedures. Rar- fifo source, erilog prepared ~ has a strong reference to the value of ~
Platform: | Size: 69632 | Author: 张勇奇 | Hits:

[OS Develop] dfifo

Description: verilog，异步一进一出的例子，空满的标志。-verilog, into an asynchronous one example, air-filled logo.
Platform: | Size: 2048 | Author: 陈虎 | Hits:

[VHDL-FPGA-Verilog] c22_FIFO

Description: 精通verilog HDL语言编程源码之8——异步FIFO设计-Proficient in language programming verilog HDL source of 8- Asynchronous FIFO Design
Platform: | Size: 2048 | Author: 李平 | Hits:

[OS Develop] fifo

Description: 基于verilog的异步fifo设计，仿真效果良好-asynchronous fifo based on zhe verilog language
Platform: | Size: 5120 | Author: 颜良飞 | Hits:

[VHDL-FPGA-Verilog] afifo

Description: verilog编写的异步FIFO代码，功能仿真时是正确的。-verilog code written in asynchronous FIFO, functional simulation is the right time.
Platform: | Size: 1024 | Author: 查乐 | Hits:

[VHDL-FPGA-Verilog] ad_da_ctr

Description: 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simulation results are basically correct.
Platform: | Size: 2299904 | Author: ych | Hits:

[VHDL-FPGA-Verilog] AsynFIFO

Description: Verilog 代码 异步FIFO，可综合，综合效率高，cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
Platform: | Size: 32768 | Author: 郑宇龙 | Hits:

[VHDL-FPGA-Verilog] FIFO-verilog

Description: 两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
Platform: | Size: 12288 | Author: 范先龙 | Hits:

[VHDL-FPGA-Verilog] Asynchronous-FIFO-Design

Description: 异步FIFO设计，一共包含6个模块，使用的硬件描述语言verilog。-Asynchronous FIFO design,including six modules.HDL language is verilog.
Platform: | Size: 3072 | Author: 林峰 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
Platform: | Size: 3072 | Author: zx | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: Verilog HDL语言编写异步FIFO-Verilog HDL language, asynchronous FIFO
Platform: | Size: 3072 | Author: 赵鑫 | Hits:

[Other] fifo

Description: 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
Platform: | Size: 175104 | Author: zhaoyibin | Hits:

[VHDL-FPGA-Verilog] asynchronous-FIFO-verilog

Description: FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write address lines, very simple to use
Platform: | Size: 14336 | Author: chenkun | Hits:

[VHDL-FPGA-Verilog] async_fifo-and-verilog

Description: 异步fifo的详细原理分析说明及verilog源代码，经典推荐！-Detailed description of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
Platform: | Size: 12288 | Author: 雨茗 | Hits:

[VHDL-FPGA-Verilog] asyn_fifo

Description: 该源码包是异步fifo的Verilog语言模型，主要包括2个部分：异步fifo控制模块、测试文件。(The source package is asynchronous FIFO Verilog language model, including 2 main parts: asynchronous FIFO control module, test files.)
Platform: | Size: 1024 | Author: 叶古 | Hits:

[VHDL-FPGA-Verilog] 异步FIFO

Description: 自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
Platform: | Size: 2048 | Author: 大黄黄黄 | Hits:

[VHDL-FPGA-Verilog] verilog实例 [43项]

Description: 一些采用verilog描述的数字功能模块，有常见的同步异步FIFO，RAM等模块，适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)
Platform: | Size: 190464 | Author: hayto | Hits:

[VHDL-FPGA-Verilog] 异步FIFO

Description: 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)
Platform: | Size: 2048 | Author: wt2110 | Hits:
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